In order to improve the density of memory device, the industry has worked extensively at developing a method for reducing the size of a two-dimensional arrangement of memory cells. As the size of the memory cells of two-dimensional (2D) memory devices continues to shrink, signal conflict and interference will significantly increase, so that it is difficult to perform operation of multi-level cell (MLC). In order to overcome the limitations of 2D memory devices, the industry has developed a memory device having a three-dimensional (3D) structure, to improve integration density by arranging the memory cells over the substrate three-dimensionally.
Due to its special three-dimensional structure and complicated process inheritance, three-dimensional memory can only use polycrystalline (silicon) materials instead of monocrystal (silicon) materials as its channel, wherein the grain size of polycrystalline (silicon) materials, the number of crystal grain boundary traps have become the key points limiting the channel conductivity. A high interface state makes the channel leakage larger, and meanwhile the impact of temperature changes on characteristics is great.
FIGS. 1 to 4 illustrate a method of manufacturing a three-dimensional memory in the prior art. Specifically, a stack comprised of different dielectric materials 2A/2B is deposited on substrate 1 to serve as a dummy gate, and then an insulating isolation layer 3 between memory cells is formed by etching openings between a plurality of dummy gate stacks and filling insulating material therein. The isolation layer 3 surrounds a plurality of active regions. The dummy gate stacks in the active regions are etched to form a plurality of channel trenches, and a layer of gate dielectric 4 is deposited into the trenches. A first amorphous channel layer 5, such as amorphous silicon, is conformally deposited on the gate dielectric 4 to act as a nucleation or interfacial layer for subsequent channel layer. The thickness of the layer 5 is very small, for example, only 0.2˜5 nm. The quality of film 5 is poor due to inhomogeneous thickness and a large number of defects exist on the surface. Then, as shown in FIG. 2, the gate dielectric 4 is etched until the substrate 1 is exposed. In this etching process, the dry etching gas not only etches away the gate dielectric 4 at the bottom of the trenches, but also laterally etches the channel layer 5, worsening the defects and damage of its surface. During deposition of a second amorphous channel layer 7 shown in FIG. 3, damage defects on the surface of the first amorphous channel layer 5 will remain, resulting in a poor amorphous-amorphous interface between second amorphous channel layer 7, as shown in thick solid line in FIG. 3. Thus, during the subsequent process of annealing the amorphous silicon for converting it into polycrystalline channel layer as shown in FIG. 4, this kind of high interfacial state will affect the properties of the polycrystalline channel layer 8/8′.